TTL circuits are derived from a common NAND logic structure of which FIG. 1 shows a conventional arrangement of the input/inverting section. In this partial TTL circuit, N logical input voltage signals V.sub.X1, V.sub.X2, . . . and V.sub.XN are provided respectively to N emitters of a multiple-emitter NPN transistor Q1 whose collector is connected to the base of a phase-splitting NPN transistor Q2. Its emitter is at a control voltage V.sub.E, while its collector provides a logical voltage signal V.sub.Y. The base of transistor Q1 is connected to a current source consisting of a resistor R1 connected to a source of a supply voltage V.sub.CC. The collector of transistor Q2 is connected to another current source consisting of a resistor R2 connected to the V.sub.CC supply.
The basic inverting operation of the TTL circuit of FIG. 1 can be understood by first assuming that all but one of input voltages V.sub.X1 -V.sub.XN are at a nominal high value V.sub.1 at logical "1" (hereafter usually just "1"). For example, let each of voltages V.sub.X2 -V.sub.XN be held at V.sub.1. Equivalently, the associated (N-1) emitters of transistor Q1 are open and thus essentially nonexistent so that transistor Q1 acts as a single-emitter transistor controlled by voltage V.sub.X1.
Next, assume that voltage V.sub.X1 is initially at a nominal low value V.sub.0 at logical "0" (hereafter usually just "0") which is sufficiently low that transistor Q1 is turned on (fully conductive). Current from the R1 current source flows into the base of transistor Q1 and out through its emitter controlled by voltage V.sub.X1. The voltage between the base and emitter of transistor Q1 is 1V.sub.BE, where V.sub.BE is the standard base-to-emitter voltage for an NPN transistor when its base-emitter junction is just conductively forward biased. The collector of transistor Q1 conducts substantially no current since transistor Q2 does not act as a current supply for transistor Q1. Nonetheless, transistor Q1 is saturated. Its collector-to-emitter voltage is V.sub.SAT1 which is near 0 volt. Transistor Q2 is turned off (non-conductive). Its base-to-emitter voltage is less than 1V.sub.BE. Voltage V.sub.Y is at a "1" level near V.sub.CC.
Voltage V.sub.X1 is now raised, causing the base and collector voltages for transistor Q1 to increase so as to keep it conductive with its collector-to-emitter voltage at V.sub.SAT1. Voltage V.sub.E normally rises also. The base voltage for transistor Q2 likewise increases until its base-to-emitter voltage reaches 1V.sub.BE. At this point, the base-collector junction of transistor Q1 becomes conductively forward biased and transmits current from the R1 source to the base of transistor Q2 to turn it on and cause it to saturate. Voltage V.sub.E reaches an upper limit V.sub.EM and normally stays there while transistor Q2 is on. Transistor Q1 turns off as its base-to-emitter voltage drops below 1V.sub.BE. Accordingly, the threshold value V.sub.TR of voltage V.sub.X1 at which transistor Q2 turns on is V.sub.EM +V.sub.BE -V.sub.SAT1. Since transistor Q2 is saturated, its collector-to-emitter voltage is V.sub.SAT2 which is near 0 volt. Voltage V.sub.Y drops to a "0" level at V.sub.EM +V.sub.SAT2. Voltage V.sub.X1 continues to rise up to V.sub.1.
Substantially the opposite occurs when voltage V.sub.X1 is brought back down to V.sub.0. As voltage V.sub.X1 drops to V.sub.EM +V.sub.BE -V.sub.SAT1, transistor Q2 turns off, and transistor Q1 turns on. Consequently, the threshold voltage V.sub.TF at which transistor Q2 turns off equals V.sub.TR. Voltage V.sub.Y returns to its "1" level. The high-level falling input noise margin V.sub.1 -V.sub.TF therefore equals the high-level rising input noise margin V.sub.1 -V.sub.TR. Likewise, the low-level input noise margins V.sub.TF -V.sub.0 and V.sub.TR -V.sub.0 are the same.
A disadvantage of the foregoing circuit is that noise in input voltage V.sub.X1 can occasionally cause the circuit to switch state more than once during a slow transition in voltage V.sub.X1. For example, noise during a slow rise in voltage V.sub.X1 could cause transistor Q2 to turn on, off, and then on again. This can largely be avoided by including hysteresis in the circuit at the switching points so that voltage V.sub.TR exceeds voltage V.sub.TF by more than the typical amount of noise in voltage V.sub.X1. Moreover, such hysteresis improves the input noise margins since the high-level falling input noise margin then exceeds the high-level rising input noise margin, while the complement of this is true for the low-level input noise margins. When voltage V.sub.X1 is at V.sub.1, an unintentional transient V.sub.X1 drop below V.sub.TR would not cause transistor Q2 to switch off unless voltage V.sub.X1 also drops below V.sub.TF. Similarly, a transient increase in voltage V.sub.X1 from V.sub.0 to V.sub.TF would not cause the circuit to switch unless voltage V.sub.X1 also rises above V.sub.TR. In short, use of such hysteresis in the TTL circuit shown in FIG. 1 would provide additional noise immunity.
B. T. Murphy et al disclose such a TTL circuit with hysteresis in "Transistor-Transistor Logic with High Packing Density and Optimum Performance at High Inverse Gain," 1968 ISSCC Dig. of Tech. Paps., Feb. 15, 1968, pp. 38-39. In this circuit, transistor Q2 is formed with an additional emitter to achieve hysteresis. This additional emitter is connected to a resistive voltage divider connected between the base and collector of transistor Q1. Even though this circuit can be implemented easily, there may be manufacturing difficulty in the control of the emitter-to-emitter gain.
The switching speed of the basic TTL circuit of FIG. 1 can be improved by utilizing appropriate clamping circuitry to keep transistor Q2 out of saturation. H. Enomoto discloses such a clamped TTL circuit in "Logical Operation Circuit", Japanese patent publication Kokai No. 54-134548, Oct. 19, 1979. In this circuit, a Schottky diode arranged in an opposing configuration to the base-emitter junction of transistor Q1 is connected between the base of transistor Q1 and the collector of transistor Q2 so as to prevent it from going into deep saturation. This circuit, however, does not contain hysteresis for providing additional noise immunity.